Holdtime correction using input/output block delay

摘要

Various techniques are provided to correct for hold time violations using input/output (I/O) block hardware of a programmable logic device (PLD) without requiring additional mapping, placement, or routing operations. In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes assigning components of the PLD to perform the operations. The method also includes routing a signal path among the components. The method also includes detecting a hold time violation for the signal path at an I/O block of the PLD. The method also includes selectively adjusting a variable delay cell of the I/O block to correct the hold time violation.

主权项

1. A method, comprising actions performed by a processor of:
receiving a design identifying operations to be performed by a programmable logic device (PLD); assigning components of the PLD to perform the operations; routing a signal path among the components; detecting a hold time violation for the signal path at an input/output (I/O) block of the PLD; characterizing an amount of delay required to correct the hold time violation for the signal path; determining a setting for a variable delay cell in the I/O block that adds the characterized amount of delay to the signal path;and
providing logic in the design of the PLD coupled with a configuration port of the variable delay cell, which applies a signal to the variable delay cell to set the variable delay cell of the I/O block according to the determined setting to correct the hold time violation.