发明名称 FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
摘要 A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
申请公布号 US2016119128(A1) 申请公布日期 2016.04.28
申请号 US201514984656 申请日期 2015.12.30
申请人 Intel Corporation 发明人 Shay Gueron;Feghali Wajdi K.;Gopal Vinodh;Makaram Raghunandan;Dixon Martin G.;Chennupaty Srinivas;Kounavis Michael E.
分类号 H04L9/06;G06F12/08;G06F12/14 主分类号 H04L9/06
代理机构 代理人
主权项 1. A system comprising: a processor comprising: a plurality of cores; a level 1 (L1) instruction cache to store a plurality of instructions, the plurality of instructions to include a first Advanced Encryption Standard (AES) instruction; an L1 data cache; instruction fetch logic to fetch instructions from the L1 instruction cache; decode logic to decode instructions; a first source register to store a round key to be used for a round of an AES decryption operation; a second source register to store input data to be decrypted by the round of the AES decryption operation; an execution unit including AES execution logic to execute the first AES instruction to perform the round of the AES decryption operation, the AES decryption operation to use the round key from the first source register to decrypt input data from the second source register and to store a result of the round of the AES decryption operation in a destination register; wherein the round of the AES decryption operation is to include: a substitution operation to be performed on the input data, the substitution operation to use an inverse substitution box (S-box), an inverse Shift Rows operation, an inverse Mix Columns operation, and an Add Round Key operation in which an exclusive OR function is to use data from the round key; a memory controller to couple the processor to a dynamic random access memory (DRAM); and an input/output (I/O) controller to couple the processor to one or more devices.
地址 Santa Clara CA US