| 主权项 |
1. A system comprising:
a processor comprising: a plurality of cores; a level 1 (L1) instruction cache to store a plurality of instructions, the plurality of instructions to include a first Advanced Encryption Standard (AES) instruction; an L1 data cache; instruction fetch logic to fetch instructions from the L1 instruction cache; decode logic to decode instructions; a first source register to store a round key to be used for a round of an AES encryption operation; a second source register to store input data to be encrypted by the round of the AES encryption operation; an execution unit including AES execution logic to execute the first AES instruction to perform the round of the AES encryption operation, the AES encryption operation to use the round key from the first source register to encrypt input data from the second source register and to store a result of the round of the AES encryption operation in a destination register; wherein the round of the AES encryption operation is to include: a Sub Bytes transform to perform a byte substitution on the input data, the Sub Bytes transform to use a substitution box (S-box) to result in a first array of substituted data, a Shift Rows transform to shift row data in the first array by a specified amount to result in a second array, a Mix Columns transform in which columns of the second array are to be treated as polynomials over a Galois Field GF(28) and multiplied modulo x4+1 with a fixed polynomial to generate a mix columns result, and an Add Round Key transform in which an exclusive OR function is to use data from the round key and the mix columns result; a system memory comprising a multiple data rate dynamic random access memory coupled to the processor over one or more interconnects; and one or more storage devices coupled to the processor. |
