| 摘要 |
A TFT array substrate in which, by means of an alteration in the layout of subpixels (P(n)), subpixels in a same frame image display period and having spatially uneven brightness are laid out in a staggered arrangement, thus overcoming display flaws in light and dark vertical lines, while also causing a reduction in overall data line (D(n)) resistance, thus reducing resistive-capacitive delay and avoiding the appearance of wrong charges at the ends of the scan lines (G(n)) or data lines (D(n)). |
