SELF-COMPENSATING GATE DRIVING CIRCUIT

摘要

The present invention provides a self-compensating gate driving circuit which comprises a plurality of GOA units which are cascade-connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area. The Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part. The pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding part are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a DC low voltage VSS.

主权项

1. A self-compensating gate driving circuit, comprising: a plurality of gate driver on array units which are cascade connected, and a Nth gate driver on array unit controls charge to a Nth horizontal scanning line in a display area, and the Nth gate driver on array unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point and the Nth horizontal scanning line, and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point, and the pull-down holding part is inputted with a DC low voltage;
the pull-down holding part comprises: a first thin film transistor, and a gate of the first thin film transistor is electrically coupled to the first circuit point, and a drain is electrically coupled to the Nth horizontal scanning line, and a source is inputted with the DC low voltage; a second thin film transistor, and a gate of the second thin film transistor is electrically coupled to the first circuit point, and a drain is electrically coupled to the Nth gate signal point, and a source is inputted with the DC low voltage; a third thin film transistor, utilizing a diode-connection, and a gate is electrically coupled to a DC signal source, and a drain is electrically coupled to the DC signal source, and a source is electrically coupled to a second circuit point; a fourth thin film transistor, and a gate of the fourth thin film transistor is electrically coupled to the Nth gate signal point, and a drain is electrically coupled to the second circuit point, and a source is inputted with the DC low voltage; a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically coupled to a N−1th gate signal point, a drain is electrically coupled to the first circuit point, and a source is inputted with the DC low voltage; a sixth thin film transistor, and a gate of the sixth thin film transistor is electrically coupled to a N+1th horizontal scan line, and a drain is electrically coupled to the first circuit point, and a source is electrically coupled to the Nth gate signal point; a first capacitor, and an upper electrode plate of the first capacitor is electrically coupled to the second circuit point and a lower electrode plate of the first capacitor is electrically coupled to the first circuit point.