FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)

摘要

A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

主权项

1. A processor, comprising:
a plurality of cores; a level 1 (L1) instruction cache to store a plurality of instructions, the plurality of instructions to include a first Advanced Encryption Standard (AES) instruction; an L1 data cache; instruction fetch logic to fetch instructions from the L1 instruction cache; decode logic to decode instructions; a first source register to store a round key to be used for a final round of an AES encryption operation; a second source register to store input data to be encrypted by the final round of the AES encryption operation; an execution unit including AES execution logic to execute the first AES instruction to perform the final round of the AES encryption operation, the final round of the AES encryption operation to use the round key from the first source register to encrypt input data from the second source register and to store a final encrypted result of the AES encryption operation in a destination register; wherein the final round of the AES encryption operation is to include: a substitution operation to be performed on the input data, the substitution operation to use a substitution box (S-box) to result in a first array of substituted data, a Shift Rows transform to shift row data in the first array by a specified amount to generate a shift rows result, and an Add Round Key transform in which an exclusive OR function is to use data from the round key and the shift rows result.