INSTRUCTIONS CONTROLLING ACCESS TO SHARED REGISTERS OF A MULTI-THREADED PROCESSOR

摘要

Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

主权项

1. A computer-implemented method of facilitating control in a multi-threaded processor, said computer-implemented method comprising:
obtaining, by the multi-threaded processor, an instruction to be executed to perform an operation, the instruction being initiated by a thread of the multi-threaded processor; initiating execution, by the multi-threaded processor, of the instruction to perform the operation, the operation comprising multiple sub-operations to be performed atomically; determining whether the instruction is to continue to execute, the determining using interlocking to determine whether the instruction has atomic access to one or more registers shared by the thread and one or more other threads of the multi-threaded processor, wherein the interlocking is to control inter-thread operations; and continuing execution of the instruction based on the interlocking indicating the instruction is to execute, the continuing execution comprising performing the operation including using at least one shared register of the one or more registers shared by the thread and the one or more other threads of the multi-threaded processor to perform the operation.