SUCCESSIVE APPROXIMATION REGISTER-BASED ANALOG-TO-DIGITAL CONVERTER WITH INCREASED TIME FRAME FOR DIGITAL-TO-ANALOG CAPACITOR SETTLING

摘要

Successive approximation register (SAR)-based analog-to-digital converters (ADCs) are provided that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. An SAR ADC (100) can include a window circuit (138) that provides the comparator output directly from the comparator (120) to the DAC (140) before the latching time of the comparator (120). After the latching time, the latched version of the comparator output is provided to the DAC capacitor (144). By providing the capacitor output to the DAC capacitor (144) before latching, the DAC capacitor (144) can settle earlier compared to the SAR ADC (100) where the DAC capacitor (144) settling begins after the latching time of the comparator (120).