NOVEL LOW POWER MINIMAL DISRUPTIVE METHOD TO IMPLEMENT LARGE QUANTITY PUSH & PULL USEFUL-SKEW SCHEDULES WITH ENABLING CIRCUITS IN A CLOCK-MESH BASED DESIGN

摘要

According to one general aspect, a method may include receiving a digital circuit model that includes models of a clock mesh and a plurality of logic circuits, each logic circuit associated with end-points of the logic circuit. The method may also include identifying a cluster of end-points, wherein the cluster is associated with a common version of the clock signal. The method may also include identifying an associated skew-schedule for each end-point. The method may include determining a timing slack and skew schedule for each end-point within the cluster. The method may include adjusting a clock-gater cell, based upon a common push/pull schedule associated with the cluster. The method may further include inserting, for at least one end-point of the cluster, a skew-buffer, wherein a variant of the skew-buffer for a respective end-point is based upon a difference between the end-point's skew schedule and the common push/pull schedule.

主权项

1. A method comprising:
receiving a digital circuit model comprising models of:
a clock mesh configured to provide a clock signal to a plurality of logic circuits, anda plurality of logic circuits, each logic circuit at least in partially controlled by an application of the clock signal to one or more end-points of the logic circuit; identifying a cluster of end-points, wherein the cluster is at least partially controlled by a common version of the clock signal and a common enable signal; identifying an associated skew-schedule for each end-point; determining a timing slack and skew schedule for each end-point within the cluster; adjusting a clock-gater cell in the digital circuit model, wherein the clock-gater cell sets a common latency for the cluster and comprises a variant of the clock-gater cell based upon a common push/pull schedule associated with the cluster; and inserting, for at least one end-point of the cluster, a skew-buffer into the digital circuit model, wherein a variant of the skew-buffer for a respective end-point is based upon a difference between the skew schedule associated with the respective end-point and the common push/pull schedule associated with the cluster.