MEMORY WITH BIT LINE CONTROL

摘要

A memory comprises a first memory cell set coupled between a first data line and a second data line. In addition, the memory comprises a first input/output (I/O) circuit coupled to the first data line and the second data line. The first I/O circuit is also coupled to a first control line to receive a first control signal, and coupled to a first select line to receive a first select signal. The first I/O circuit selectively decouples the first data line and the second data line from the first I/O circuit during a sleep mode based on the first control signal and the first select signal.