发明名称 情報処理装置
摘要 According to one embodiment, an information processing apparatus includes a processor, a main memory, and a memory controller. The memory controller executes an access restriction for each memory region. A first program decodes a protected program which was encrypted in a secure mode. The first program places the protected program which was decoded in a memory region. A second program executes the protected program in a secure mode. The processor places a code region and a protected data region in the protected program which was decoded in a memory region having an access restriction by using the first program. When an access to the protected data region is confirmed, the processor confirms by using the second program that the access is caused by a command from the code region placed by the first program, and then, executes the command.
申请公布号 JP5911835(B2) 申请公布日期 2016.04.27
申请号 JP20130191382 申请日期 2013.09.17
申请人 株式会社東芝 发明人 佐野 伸太郎;佐々木 俊介;磯崎 宏;金井 遵;岐津 俊樹;奈良 竜太
分类号 G06F21/12;G06F12/14;G06F21/14;G06F21/62 主分类号 G06F21/12
代理机构 代理人
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