| 摘要 |
Successive blocks of an input signal are fed to M respective delta-sigma modulator channels 11, in which the output FIFOs 17 are filled at a rate that is about 1/M of the rate at which the contents of these FIFOs 17 are read through the multiplexer 20. This use of multiple parallel channels allows a lower clock rate to be used, so that delta-sigma modulators for switching UHF amplifiers become practical. Transients that may be evident upon a changeover between channels are reduced by overlaps (figure 5). The channels may be reset between the processing of data blocks, so that instability, to which high-order delta-sigma modulators are susceptible, does not have time to arise. The modulator may be used in class-S RF amplifiers or in analogue-to-digital converters. |
