AIR GAP SPACER INTEGRATION FOR IMPROVED FIN DEVICE PERFORMANCE

摘要

Provided is a method for providing a FinFET device that has an air gap spacer. The present invention includes: a step of providing a substrate that has a first interlayer dielectric (ILD) layer, a plurality of fins, and a dummy polysilicon gate arranged across the fins; a step of depositing a sacrificial spacer at a circumference of the dummy polysilicon gate; a step of depositing a second ILD layer at a circumference of the sacrificial spacer; a step of selectively etching the dummy polysilicon gate with respect to the second ILD layer and the sacrificial spacer; a step of depositing a replacement metal gate (RMG); a step of etching a part of the RMG such that a recess surrounded by the sacrificial spacer is generated; and a step of depositing a gate capping layer with a first layer surrounded by the sacrificial spacer at least in part, as a step of depositing the gate capping layer in the recess. The gate capping layer is made of silicon oxycarbide (SiOC).