Requalization effort-balancing of transmit finite impulse response and receive linear equalizer or receive decision feedback equalizer structures in high-speed serial interconnects

摘要

Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link having a plurality of lanes is detected. At least one of the plurality of the transmit equalization values and at least one of the plurality of the receive equalization values are selected for each lane of the plurality of lanes of the link based on detection of saturation in a Decision Feedback Equalizer (DFE) tap of a corresponding lane of the link. Other embodiments are also claimed and/or disclosed.

主权项

1. An apparatus comprising:
hardware logic to detect data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link; and hardware logic to determine which of the plurality of the transmit equalization values and which of the plurality of the receive equalization values are to be selected for each lane of a plurality of lanes of the link based at least in part on presence or absence of saturation in one or more of the plurality of lanes of the link, wherein the plurality of transmit equalization values correspond to a transmit Finite Impulse Response (FIR) filter, wherein the plurality of receive equalization values correspond to a receive Decision Feedback Equalizer (DFE) filter.