Automatic selection of on-chip clock in synchronous digital systems

摘要

Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed.

主权项

1. A synchronous digital system comprised on a chip, the synchronous digital system comprising:
synchronous digital logic configured to operate using a primary clock signal; an on-chip clock signal generator configured to generate a first clock signal independent of an external clock signal received by the synchronous digital system; and clock signal selector circuitry configured to select between a plurality of clock signals for use as the primary clock signal, wherein the plurality of clock signals comprises the first clock signal and a signal dependent on the external clock signal, wherein the clock signal selector circuitry is further configured to:
when a clock selection override signal indicates normal operation, select between the plurality of clock signals based at least in part on the contents of a software-configurable register; andwhen the clock selection override signal indicates a condition requiring selection of a clock signal generated on-chip for use as the primary clock signal, select the first clock signal;wherein the clock selection override signal comprises a tamper detection signal, and wherein the clock selection override signal indicating a condition requiring selection of a clock signal generated on-chip for use as the primary clock signal comprises the tamper detection signal indicating possible tampering with the synchronous digital system.