Semiconductor memory device having an output buffer controller

摘要

A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the data output terminal, and a calibration circuit to output an n-bit first code signal for controlling each of the n first transistors. In some embodiments, the calibration circuit includes a first counter circuit to output a k-bit second code signal (k is a natural number less than n), and a first code conversion circuit to convert the k-bit second code signal to the n-bit first code signal. Additional apparatus, systems, and methods are disclosed.

主权项

1. A semiconductor device comprising:
a data output terminal; an output buffer including n first transistors connected in parallel with the data output terminal, wherein n is a natural number greater than 1; and a calibration circuit to output an n-bit first code signal to control each of the n first transistors, wherein the calibration circuit includes a first counter circuit to output a k-bit second code signal, and a first code conversion circuit to convert the k-bit second code signal to the n-bit first code signal, wherein k is a natural number less than n, and wherein current drive capabilities of the n first transistors are weighted by the power of 2.