Sense amplifiers and memory devices having the same

摘要

In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.

主权项

1. A sense amplifier, comprising:
a switching transistor configured to apply a ground voltage to a ground node in response to a sense enable signal; a first detection circuit coupled between the ground node and a first detection node, the first detection circuit being configured to provide a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line; a second detection circuit coupled between the ground node and a second detection node, the second detection circuit being configured to provide a second detection signal to the second detection node based on a voltage of a complementary bit-line; a latch circuit connected to a supply voltage, the first detection node and the second detection node, the latch circuit being configured to,
generate a first amplified signal and a second amplified signal based on the first and second detection signals,output the first amplified signal through a latch node, and output the second amplified signal through a complementary latch node; and wherein the mode signal has a first logic level in a double-ended read mode, and has a second logic level in a single-ended read mode, the first logic level being different from the second logic level.