Processor, information processing apparatus, and control method of processor

摘要

A processor includes: a primary cache memory; an instruction control unit that issues a store request to the primary cache memory; a pipeline processing unit that, upon receiving the store request, writes data to the primary cache memory; a buffer unit that obtains an address output to the primary cache memory from the pipeline processing unit during an output period of the store request regarding certain data to hold the obtained address in an entry, and when the output period ends, issues a write-back request for writing the data indicated by the address held in the entry to a memory; and a secondary cache memory that, upon receiving the write-back request from the buffer unit, writes the data of the primary cache memory to the memory, the certain data is quickly written back to the memory from the primary cache memory.

主权项

1. A processor comprising:
a cache memory; an instruction control unit that issues a store request for writing data to the cache memory and respectively outputs a first signal and a second signal, wherein the instruction control unit asserts the first signal when an output of the store request regarding certain data is started and negates the first signal when the output of the store request regarding the certain data is ended, and asserts the second signal when the output of the store request regarding the certain data is ended; a first write processing unit that, upon receiving the store request from the instruction control unit, outputs an address and data of the store request to the cache memory to write the data to the cache memory; a buffer unit that includes a plurality of entries, and when the first signal is asserted, obtains the address output to the cache memory from the first write processing unit to hold the obtained address in an entry out of the plurality of entries, and when the second signal is asserted, issues a write-back request for writing, to a main storage, the data indicated by the address held in the entry; and a second write processing unit that, upon receiving the write-back request from the buffer unit, obtains the data corresponding to the write-back request from the cache memory to write the obtained data to the main storage.