Data receivers and methods of implementing data receivers in an integrated circuit

摘要

A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

主权项

1. A data receiver implemented in an integrated circuit, the data receiver comprising:
an input receiving a data signal; a phase locked loop configured to generate a reference clock signal; a first equalization circuit configured to receive the data signal, wherein the first equalization circuit is used to receive data of the data signal; a first register coupled to an output of the first equalization circuit; a first phase interpolator configured to receive the reference clock signal, wherein the first phase interpolator is configured to control the first register using a first clock signal; a second equalization circuit configured to receive the data signal; a second register coupled to an output of the second equalization circuit; and a second phase interpolator configured to receive the reference clock signal, wherein the second phase interpolator is configured to control the second register using a second clock signal that is different than the first clock signal, wherein the first clock signal is generated separately from the second clock signal, and wherein the second phase interpolator enables adjusting a clock phase offset associated with drifting of the reference clock signal; wherein the second equalization circuit is different than the first equalization circuit; and wherein the first phase interpolator enables a first function of said controlling the first register using the first clock signal while the second phase interpolator enables a second function of said adjusting the clock phase offset using the second clock signal.