Gate driver and display device using the same

摘要

A gate driver comprises an ith stage gate driver circuit including a latch circuit and a first output circuit. The latch circuit includes a first input for receiving an (i−1)th gate signal, a second input for receiving a first clock signal, a first output for outputting a first output signal, and a second output for outputting a second output signal. The first output circuit comprises a first transistor, a second transistor and a capacitor. The first transistor includes a control terminal coupled to the first output, a first terminal coupled to a first clock input and a second terminal coupled to a first output node. The second transistor includes a control terminal coupled to the second output, a first terminal coupled to the first output node and a second terminal coupled to a reference signal. The capacitor is coupled between the first transistor and the first output node.

主权项

1. A gate driver, comprising:
a plurality of gate driver circuits cascade-connected to each other, for outputting a plurality of first gate signals sequentially, wherein an ith stage gate driver circuit of the gate driver circuits, where i is an integer, comprises:
a latch circuit including:
a first input for receiving an (i−1)th gate signal of the gate signals from an (i−1)th stage gate driver circuit of the gate driver circuits;a second input for receiving a first clock signal;a first output for outputting a first output signal in response to the (i−1)th gate signal and the first clock signal; anda second output for outputting a second output signal being an inverted signal of the first output signal; anda first output circuit for outputting an ith first gate signal, comprising:
a first transistor including a control terminal coupled to the first output, a first terminal coupled to a first clock input for receiving a second clock signal and a second terminal coupled to a first output node for outputting the ith first gate signal;a second transistor including a control terminal coupled to the second output, a first terminal coupled to the first output node and a second terminal coupled to a reference signal; anda capacitor coupled between the control terminal of the first transistor and the first output node.