| 摘要 |
A semiconductor integrated circuit includes a bus, a memory connected to the bus, an arithmetic processing unit connected to the bus, a first DMA controller connected to the bus, and at least one functional block connected to the bus. The functional block includes a functional macro which is configured to perform a process that realizes a given function, a second DMA controller which is configured to control data transfer between the memory and the functional macro, and an access condition setting unit which is configured to set an access condition regarding the DMA transfer between the memory and the functional macro. |
| 主权项 |
1. A semiconductor integrated circuit comprising:
a bus; a memory connected to the bus; an arithmetic processing unit connected to the bus; a first DMA controller connected to the bus; and at least one functional block connected to the bus, the functional block including a functional macro which is configured to perform a process that realizes a given function, a second DMA controller which is configured to control data transfer between the memory and the functional macro, and an access condition setting circuit which is configured to set an access condition regarding the data transfer between the memory and the functional macro controlled by the second DMA controller, wherein the access condition setting circuit includes a first register and a control code storing circuit, the first register is configured to set the access condition including an address of the memory and transfer size in a unit of instruction, the control code storing circuit is configured to store a control code, at least one of the first register and the control code storing circuit is further configured to set an address of a second register in the first DMA controller, and the second register is configured to set status information of the first DMA controller, and the second DMA controller is configured to control an access to the memory by the second DMA controller by determining whether the first DMA controller is performing transfer process or is in an idle state in accordance with the status information of the first DMA controller read from the second register by using the address of the second register, the access condition in the first register set in the unit of instruction, and the control code stored in the control code storing circuit, when an access to the memory conflicts with an access by the first DMA controller. |
