发明名称 Systems, apparatuses, and methods for determining a trailing least significant masking bit of a writemask register
摘要 The execution of a KZBTZ finds a trailing least significant zero bit position in an first input mask and sets an output mask to have the values of the first input mask, but with all bit positions closer to the most significant bit position than the trailing least significant zero bit position in an first input mask set to zero. In some embodiments, a second input mask is used as a writemask such that bit positions of the first input mask are not considered in the trailing least significant zero bit position calculation depending upon a corresponding bit position in the second input mask.
申请公布号 US9323531(B2) 申请公布日期 2016.04.26
申请号 US201313840809 申请日期 2013.03.15
申请人 Intel Corporation 发明人 Hughes Christopher J.;Charney Mark J.;Corbal Jesus;Girkar Milind B.;Ould-Ahmed—Vall Elmoustapha;Toll Bret L.;Valentine Robert
分类号 G06F9/30;G06F9/40;G06F15/00 主分类号 G06F9/30
代理机构 Nicholson De Vos Webster & Elliott LLP 代理人 Nicholson De Vos Webster & Elliott LLP
主权项 1. An apparatus comprising: decode logic to decode an instruction, the instruction including a first source writemask operand and a destination writemask operand; execution logic to execute the decoded instruction to find a trailing least significant zero bit position in the first source writemask operand and set the destination writemask operand to have values of the first source writemask operand, but with all bit positions closer to a most significant bit position than a trailing least significant zero bit position in the first source writemask operand set to zero.
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