发明名称 Memory unit and method of testing the same
摘要 A memory unit that includes a tracking unit, a scan chain and a scan chain control unit. The tracking unit includes a tracking bit line, wherein the tracking unit is configured to receive a tracking control signal, selectively charge or discharge a voltage on the tracking bit line in response to the tracking control signal and generate a sense amplifier signal. The scan chain includes one or more logic devices, wherein the scan chain is configured to receive at least a first control signal. The scan chain control unit is connected to the scan chain and the tracking unit. The scan chain control unit is configured to receive the sense amplifier signal and generate the first scan chain control signal.
申请公布号 US9324453(B2) 申请公布日期 2016.04.26
申请号 US201414222018 申请日期 2014.03.21
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Hsieh Wei-Jer;Cheng Hong-Chen;Cheng Chiting;Lin Yangsyu;Lee Cheng Hung;Chang Jonathan Tsung-Yung
分类号 G11C11/00;G11C29/32;G11C11/41 主分类号 G11C11/00
代理机构 Hauptman Ham, LLP 代理人 Hauptman Ham, LLP
主权项 1. A memory unit, comprising: a tracking unit comprising a tracking bit line, wherein the tracking unit is configured to: receive a tracking control signal;selectively charge or discharge a voltage on the tracking bit line in response to the tracking control signal; andgenerate a sense amplifier signal; a scan chain, wherein the scan chain comprises one or more logic devices, wherein the scan chain is configured to receive at least a first control signal; and a scan chain control unit connected to the scan chain and the tracking unit, wherein the scan chain control unit is configured to: receive the sense amplifier signal; andgenerate a first scan chain control signal.
地址 TW