Multi-die memory device

摘要

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

主权项

1. A memory comprising:
a logic die including a serial interface having plural transmitters; a first memory die stacked on the logic die and coupled to the serial interface; and wherein the serial interface includes
mode select logic responsive to an interface select signal to, in a first mode of operation, activate all of the plural transmitters for transmitting serialized read data to a memory controller at a first data rate, and in a second mode of operation, activate less than all of the plural transmitters for transmitting serialized read data to the memory controller at a second data rate that is different than the first data rate.