发明名称 |
Flip-flop layout architecture implementation for semiconductor device |
摘要 |
A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode. |
申请公布号 |
US9324715(B2) |
申请公布日期 |
2016.04.26 |
申请号 |
US201414504075 |
申请日期 |
2014.10.01 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
Azmat Raheel;Sengupta Rwik;Park Chulhong;Chun Kwanyoung |
分类号 |
H01L27/092;H01L27/02;H01L21/8238 |
主分类号 |
H01L27/092 |
代理机构 |
Muir Patent Law, PLLC |
代理人 |
Muir Patent Law, PLLC |
主权项 |
1. A semiconductor device, comprising:
a substrate including a PMOSFET region and an NMOSFET region; a first and a second gate electrode in the PMOSFET region; a third and a fourth gate electrode in the NMOSFET region; a connection contact connecting the second gate electrode and the third gate electrode, wherein the connection contact is electrically connected with upper surfaces of the second and third gate electrodes; and a connection line connecting the first gate electrode and the fourth gate electrode, the connection line crossing over the connection contact. |
地址 |
Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do KR |