Integrated circuit wafer having integrated circuit die with plural comparators receiving expected data and mask data from different pads

摘要

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

主权项

1. An integrated circuit wafer comprising:
A. a first integrated circuit die including:
i. input pads and output pads;ii. first core circuitry having inputs coupled to the input pads and outputs coupled to the output pads, the first core circuitry including a first core output coupled to a first output pad, and the first core circuitry including a second core output coupled to a second output pad;iii. first comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first output pad, a mask data input coupled to a third output pad, a compare strobe input coupled to a compare strobe lead, a scan data input, a scan data output, and a scan control input coupled to a scan control lead; andiv. second comparator circuitry having an input coupled to the second core output, an expected data input coupled to the second output pad, a mask data input coupled to a fourth output pad, a compare strobe input coupled to the compare strobe lead, a scan data input coupled to the scan data output of the first comparator circuitry, a scan data output, and a scan control input coupled to the scan control lead; and B. a second integrated circuit die formed separate from the first integrated circuit die on the wafer, the second integrated circuit die including:
i. input pads and output pads;ii. second core circuitry having inputs coupled to the input pads and outputs coupled to the output pads, the second core circuitry including a first core output coupled to a first output pad, and the second core circuitry including a second core output coupled to a second output pad;iii. third comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first output pad, a mask data input coupled to a third output pad, a compare strobe input coupled to a compare strobe lead, a scan data input, a scan data output, and a scan control input coupled to a scan control lead; andiv. fourth comparator circuitry having an input coupled to the second core output, an expected data input coupled to the second output pad, a mask data input coupled to a fourth output pad, a compare strobe input coupled to the compare strobe lead, a scan data input coupled to the scan data output of the first comparator circuitry, a scan data output, and a scan control input coupled to the scan control lead.