发明名称 Gate dielectric protection for transistors
摘要 At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.
申请公布号 US9324822(B2) 申请公布日期 2016.04.26
申请号 US201414321679 申请日期 2014.07.01
申请人 GLOBALFOUNDRIES INC. 发明人 Kerber Andreas;Uppal Suresh;Cimino Salvatore;Jiang Hao
分类号 H01L29/00;H01L21/00;H01L29/423;H01L21/66;H01L29/08;H01L21/28;H01L21/762;H01L29/06;H01L29/49;H01L29/66;H01L29/78;G01R31/26 主分类号 H01L29/00
代理机构 Williams Morgan, P.C. 代理人 Williams Morgan, P.C.
主权项 1. A method for forming a transistor, comprising: forming a source region on a substrate, comprising forming a first n+dopant region on a p-type substrate and forming a first contact region above said first n+dopant region; forming a drain region on said substrate adjacent said active gate region, comprising forming a second n+dopant region on said p-type substrate and forming a second contact region above said second n+dopant region; forming an active gate region on said substrate adjacent said source region, comprising forming a first gate oxide region above said p-type substrate between said first and second n+dopant regions and forming a first polysilicon conductor region above said first gate oxide region; and forming a first inactive gate region on said substrate in parallel to said active gate region, comprising forming a second gate oxide region above said p-type substrate adjacent said first n+dopant region, forming a second polysilicon conductor region above second first gate oxide region, and electrically coupling said second polysilicon conductor region to said first polysilicon conductor region, wherein said source region, said drain region, said active gate region, and said first inactive gate region comprise said transistor, and wherein said first inactive gate region is capable of dissipating at least a portion of a charge.
地址 Grand Cayman KY