Systems and methods for transferring a signal from a first clock domain to a second clock domain

摘要

Systems and methods are provided for transferring a signal from a first clock domain to a second clock domain. A system includes a pulse generator configured to receive an input data signal in the first clock domain and to generate a pulse. The system further includes an unclocked flip-flop configured to generate a first output signal. The first output signal is received by a circuit operating in the second clock domain, and the first output signal has one of a first logical value and a second logical value. The unclocked flip-flop is configured to set the first output signal to the first logical value in response to the pulse. The unclocked flip-flop is configured to reset the first output signal to the second logical value in response to a clock signal in the second clock domain and a second output signal generated by the circuit.

主权项

1. A system for transferring a signal from a first clock domain to a second clock domain, the system comprising:
a metastability detector configured to detect a metastability state between circuitry in a first clock domain and circuitry in a second clock domain, the metastability state occurring when the circuitry in the second clock domain receives an input data signal in the first clock domain that violates a timing requirement of the circuitry in the second clock domain, the metastability detector being configured to (i) determine a relationship between the input data signal and a clock signal of the second clock domain, and (ii) detect the metastability state based on the relationship; and a metastability mitigator configured to force the circuitry in the second clock domain out of the metastability state to a correct logic level value in response to the metastability state being detected.