发明名称 Lane error detection and lane removal mechanism to reduce the probability of data corruption
摘要 Method, apparatus, and systems for detecting lane errors and removing errant lanes in multi-lane links. Data comprising link packets is split into a plurality of bitstreams and transmitted over respective lanes of a multi-lane link in parallel. The bitstream data is received at multiple receive lanes of a receiver port and processed to reassemble link packets and to calculate a CRC over the data received on each lane. The link packets include a transmitted CRC that is compared to a received CRC to detect link packet errors. Upon detection of a link packet error, per-lane or per transfer group CRC values are stored, and a retry request is issued to retransmit the bad packet. In conjunction with receipt of the retransmitted packet, per-lane or per transfer group CRC values are recalculated over the received data and compared with the stored per-lane or per transfer group CRC values to detect the lane causing the link packet error.
申请公布号 US9325449(B2) 申请公布日期 2016.04.26
申请号 US201314099345 申请日期 2013.12.06
申请人 Intel Corporation 发明人 Birrittella Mark S.
分类号 H03M13/00;G06F11/10;H04L1/00;H03M13/09 主分类号 H03M13/00
代理机构 Law Office of R. Alan Burnett, P.S. 代理人 Law Office of R. Alan Burnett, P.S.
主权项 1. An apparatus, comprising: a link interface including, a receive port comprising a plurality of receive lanes, each configured to receive a respective bitstream of a plurality of bitstreams transmitted in parallel from a transmit port of a link interface peer; and circuitry and logic to, process the plurality of bitstreams as they are received and extract data comprising link packets transmitted from the link interface peer;detect a bad received link packet; anddetect an errant receive lane that caused the bad received link packet.
地址 Santa Clara CA US