| 发明名称 | Memory architecture | ||
| 摘要 | A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit. | ||
| 申请公布号 | US9324412(B2) | 申请公布日期 | 2016.04.26 |
| 申请号 | US201313791025 | 申请日期 | 2013.03.08 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 发明人 | Katoch Atul;Tayal Mayank |
| 分类号 | G11C7/22;G11C11/419;G11C7/08;G11C7/12 | 主分类号 | G11C7/22 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A memory circuit comprising: a memory cell; a first write switching circuit; a first data line; and a data circuit, wherein a first terminal of the first write switching circuit is coupled with a first output of the data circuit;the first data line is associated with a first node of the memory cell and is coupled with a second terminal of the first write switching circuit;in a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to a second output of the data circuit; the first write logical value different from the second write logical value; andthe memory cell is configured to receive data from the first output and the second output as data to be written into the memory cell; andin a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit, and the first data line is pre-charged to the same logical value in the read operation. | ||
| 地址 | TW | ||