| 摘要 |
The present invention relates to a semiconductor device and, more particularly, to a circuit for decoding an address input to a semiconductor memory device. The address decoding circuit according to the present invention comprises: a main address processing unit configured to latch a main address in response to a latch signal and to output the latched main address; a repair unit configured to determine whether the main address corresponds to a defective region and to output a repair address and a repair signal based on a result of the determination; a synchronization unit configured to synchronize the latched main address, the repair address and the repair signal with a synchronization signal and to output the synchronized main address, the synchronized repair address and the synchronized repair signal; and a decoder configured to decode any one of the synchronized main address and the synchronized repair address in response to a decoding signal. |
