Three-dimensional vertical gate NAND flash memory including dual-polarity source pads

摘要

A memory includes a three-dimensional array including a plurality of levels is described. Each level includes a bit line pad, a source line pad, and a plurality of strips of semiconductor material extending between the bit line pad and the source line pad. The source line pad includes at least one n-type region and at least one p-type region. The memory includes word lines coupled to the plurality of strips in the plurality of levels. The memory includes data storage elements between the word lines and the strips of semiconductor material, whereby memory cells are disposed at cross-points of the strips and the word lines. The memory also includes circuitry coupled to the n-type region and the p-type region of the source line pad, configured to selectively enable current flow in the strips extending from the source line pad and one of the n-type region and the p-type region.

主权项

1. A memory comprising:
a strip of semiconductor material extending between a bit line pad and a source line pad, the source line pad including at least one n-type region and at least one p-type region; a gate coupled to the strip; a data storage element between the gate and the strip, whereby a memory cell is disposed at a cross-point of the strip and the gate; and circuitry coupled to the n-type region and the p-type region of the source line pad, configured to selectively enable current flow in the strip through one of the n-type region and the p-type region.