Core circuitry, test access mechanism, scan frame input register, decompressor

摘要

Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

主权项

1. An integrated circuit comprising;
A. core circuitry having scan paths, the scan paths including scan data input leads, scan data output leads, and scan control input leads; and B. a test access mechanism having: i. a serial data input lead, ii. a serial data output lead, iii. parallel data output leads coupled to the to the scan data input leads, iv. parallel data input leads coupled to the scan data output leads, v. control output leads coupled to the scan control input leads, vi. a clock signal input; vii. a functional clock signal input; viii. a test/read input, ix. a test access mechanism enable input, x. a scan frame input register having a scan frame input lead connected with the serial data input lead, the scan frame input register including a compressed stimulus section having data output leads, a command section, and a frame marker section connected in series with the serial data input lead, xi. a scan frame copy register having an output coupled with the serial data output lead, the scan frame copy register being coupled to the compressed stimulus section, the command section, and the frame marker section of the scan frame input register, and xii. compressed stimulus register and decompressor circuitry having inputs coupled with the data output leads of the of the compressed stimulus section and parallel outputs coupled with the parallel data output leads.