发明名称 Metastability prediction and avoidance in memory arbitration circuitry
摘要 An integrated circuit with hazard prediction and prevention circuitry is provided. The hazard prediction circuitry may predict a future hazard condition between two periodic signals, and the hazard prevention circuitry may selectively delay at least one of the two periodic signals to avoid the predicted hazard condition. Single-port memory cells may provide multiport memory functionality using an arbitration circuit that includes the hazard prediction and prevention circuitry and receives memory access requests from at least two request generators. The arbitration circuit may operate in synchronous mode and perform port selection based on a predetermined logic table. The arbitration circuit may also operate in asynchronous mode and execute a memory access request as soon as it is received by the arbitration circuit. Metastability caused by receiving memory access requests at the same time from at least two request generators may be avoided with the hazard prediction and prevention circuitry.
申请公布号 US9323285(B2) 申请公布日期 2016.04.26
申请号 US201313966130 申请日期 2013.08.13
申请人 Altera Corporation 发明人 Lewis David
分类号 G06F1/08;G11C7/10;G11C7/22 主分类号 G06F1/08
代理机构 代理人
主权项 1. Circuitry comprising: a first input that receives a first periodic signal having a first period; a second input that receives a second periodic signal having a second period; hazard prediction circuitry that predicts a future hazard condition between the first and second periodic signals, wherein the hazard prediction circuitry predicts the future hazard condition at a first instant of time, and the future hazard condition is predicted to occur at a second instant of time that is after the first instant of time; and hazard prevention circuitry that selectively delays at least one of the first and second periodic signals by a first predetermined duration during at least one clock cycle of the respective periodic signal prior to the second instant of time.
地址 San Jose CA US