发明名称 TRANSMITTER/RECEIVER CIRCUIT, INTEGRATED CIRCUIT AND TEST METHOD
摘要 PROBLEM TO BE SOLVED: To provide a transmitter/receiver circuit capable of inspecting jitter tolerance during a loop-back test in simple configuration, an integrated circuit and a test method.SOLUTION: The transmitter/receiver circuit includes: a phase compensator which generates a processing clock of a desired phase on the basis of a reference clock; a first selection part which selects the processing clock as a first clock in a normal mode and selects the reference clock as the first clock in a test mode; a deserializer by which serial input data are converted into parallel output data and outputted in accordance with the first clock that is selected by the first selection part; a second selection part which selects the reference clock as a second clock in the normal mode and selects the processing clock as the second clock in the test model; and a serializer by which parallel input data are converted into serial output data and outputted in accordance with the second clock that is selected by the second selection part.SELECTED DRAWING: Figure 3
申请公布号 JP2016063430(A) 申请公布日期 2016.04.25
申请号 JP20140190471 申请日期 2014.09.18
申请人 SOCIONEXT INC 发明人 TSUCHIYA NAOTO
分类号 H04L7/00;G01R31/28;H04L7/033 主分类号 H04L7/00
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