发明名称 LAMINATED SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF
摘要 PROBLEM TO BE SOLVED: To provide a structure of an interlayer wiring advantageous for the implementation of high integration of a circuit and a manufacturing method, in a laminated semiconductor element improved in an integration degree by three-dimensionally laminating a semiconductor circuit.SOLUTION: In at least one single layer semiconductor circuit constituting a laminated semiconductor element, an interlayer wiring penetrating through first and second main surfaces of the single layer semiconductor circuit is formed by: an impurity diffusion semiconductor layer formed simultaneously with the formation of a source/drain region of a transistor; a metal wiring connected to the impurity diffusion semiconductor layer and exposed to the first main surface of the single layer semiconductor circuit; and a metal wiring exposed to the second main surface of the single layer semiconductor circuit.SELECTED DRAWING: Figure 1
申请公布号 JP2016062903(A) 申请公布日期 2016.04.25
申请号 JP20140186694 申请日期 2014.09.12
申请人 NIPPON HOSO KYOKAI <NHK> 发明人 IGUCHI YOSHINORI
分类号 H01L21/3205;H01L21/768;H01L21/8234;H01L23/522;H01L27/00;H01L27/088;H01L29/786 主分类号 H01L21/3205
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