发明名称 PHASE CONTROL CIRCUIT AND RECEIVER
摘要 PROBLEM TO BE SOLVED: To accurately adjust a phase of an output signal.SOLUTION: A phase interpolation circuit 2 includes transistors T7 and T8, connected between a power supply VDD and output terminals P5 and P6, and outputs output signals Vo1 and Vo1x, having second phases, from the output terminals P5 and P6 by adding a plurality of input signals Vi1, Vi1x, Vi2, and Vi2x, having mutually different first phases, based on a ratio of a plurality of input bias currents I1 and I2. A bias circuit 3 controls on-resistance by adjusting gate voltages of the transistor T7 and T8, based on the amount value of the plurality of input bias currents I1 and I2, and maintains an output common voltage of the phase interpolation circuit 2, regardless of the amount value. A current control part 4 controls slew rate of the output signals Vo1 and Vo1x, corresponding to the plurality of input signals Vi1, Vi1x, Vi2 and Vi2x, by adjusting the amount value.SELECTED DRAWING: Figure 1
申请公布号 JP2016063402(A) 申请公布日期 2016.04.25
申请号 JP20140189944 申请日期 2014.09.18
申请人 FUJITSU LTD 发明人 CHAIVIPAS WINE
分类号 H03K5/13;H03K5/131 主分类号 H03K5/13
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