| 摘要 |
PROBLEM TO BE SOLVED: To reduce current consumption and noise.SOLUTION: A bus interface circuit is provided in each of a plurality of slave devices to which a common data stream and a clock are supplied from a master device. The bus interface circuit includes a header information detection circuit, an internal clock control circuit and a data analysis circuit. The header information detection circuit detects header information indicating a head of the data stream from the data stream including the header information, destination information indicating a destination of the data stream and a data body in this order. The internal clock control circuit outputs an internal clock that is synchronized with the clock after the header information is detected. The data analysis circuit detects the destination information from the data stream synchronously with the internal clock after the header information is detected, and then analyzes the data body in the data stream. The internal clock control circuit stops outputting the internal clock in the case where the destination in the destination information is not the bus interface circuit per se.SELECTED DRAWING: Figure 2 |
