发明名称 MONITOR CIRCUIT, LOGIC ANALYSIS TERMINAL AND SYSTEM, AND DELAY MEASURING METHOD AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To dispense with a measuring apparatus for external observation by facilitating the observation of an observation object signal without reducing the degree of freedom in arrangement and wiring.SOLUTION: The monitor circuit includes: a first multiplexer that receives observation object signals of an observation object node, and selects and outputs one observation object signal in response to a first selective signal; and a second multiplexer that receives a plurality of clock signals, and selects and outputs one clock signal in response to a second selective signal. At least one of the first and second multiplexers includes a multiplexer for suppressing the propagation of a glitch to the output when the polarity of at least one signal input of a plurality of signal inputs changes.SELECTED DRAWING: Figure 13
申请公布号 JP2016062351(A) 申请公布日期 2016.04.25
申请号 JP20140190382 申请日期 2014.09.18
申请人 NEC CORP 发明人 TAKAHASHI NAOKI
分类号 G06F11/22;G01R31/28;H01L21/82 主分类号 G06F11/22
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