CHARGE TRAPPING SPLIT GATE EMBEDDED FLASH MEMORY AND ASSOCIATED METHODS

摘要

Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.

主权项

1. A method of making a semiconductor device, comprising:
forming a dielectric layer at a first region and a second region of a semiconductor substrate; disposing a gate conductor layer over the dielectric layer formed in the first and second regions of the semiconductor substrate; masking the second region; forming a split gate memory cell in the first region of the semiconductor substrate, wherein the split gate memory cell has a first gate length; masking the first region; and etching the second region to define a logic gate, wherein the logic gate has a second gate length.