发明名称 PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA
摘要 A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.
申请公布号 US2016112049(A1) 申请公布日期 2016.04.21
申请号 US201514983968 申请日期 2015.12.30
申请人 Kabushiki Kaisha Toshiba 发明人 Yasuda Shinichi;Tatsumura Kosuke;Matsumoto Mari;Zaitsu Koichiro;Oda Masato
分类号 H03K19/177 主分类号 H03K19/177
代理机构 代理人
主权项 1. A programmable logic circuit comprising: a plurality of first wiring lines; a plurality of second wiring lines intersecting with the first wiring lines in intersecting areas; a plurality of third wiring lines; a plurality of cells provided in the intersecting areas, at least one of the cells including a first transistor with a source, a drain, and a gate, and a programmable device with a first terminal and a second terminal, the first terminal connecting to one of the source and the drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain of the first transistor being connected to one of the first wiring lines, and the gate of the first transistor being connected to one of the third wiring lines; a plurality of first cut-off transistors each including a source and a drain, one of the source and the drain being connected to the one of the second wiring lines; a plurality of first CMOS inverters corresponding to the first cut-off transistors, each of the first CMOS inverters including an input terminal, the input terminal being connected to the other of the source and the drain of the corresponding one of the first cut-off transistors.
地址 Tokyo JP