发明名称 METHOD FOR MANUFACTURING WAFER LEVEL PACKAGING DEVICE
摘要 Provided is a method for manufacturing a wafer level package device. The method of manufacturing a wafer level package device according to the present invention includes the processes of: forming a TSV pattern at a predetermined location of a silicon structure layer after preparing a silicon on glass (SOG) substrate; forming a seed layer on an insulation layer after forming the insulation layer on a surface of the SOG substrate on which the TSV pattern is formed; polishing an electroplated layer except for a portion of the electroplated layer filled in the TSV pattern after electroplating the surface of the SOG substrate on which the seed layer is formed to be filled with the formed TSV pattern; forming a sensor electrode having a predetermined pattern on the substrate, and then forming an insulation layer on the surface thereof; forming a sensor at a predetermined position of the substrate surface, and then forming a metallic solder layer in an upper portion of the TSV pattern; allowing a cap substrate having a cavity in which a sensor is accommodated, to adhere to a lower portion of the prepared substrate; and polishing and removing a glass carrier layer of the SOG substrate.
申请公布号 KR101613412(B1) 申请公布日期 2016.04.21
申请号 KR20150052228 申请日期 2015.04.14
申请人 U ELECTRONICS CO., LTD. 发明人 KIM, HYUNG WON;ANH, MI SOOK
分类号 H01L25/07;H01L21/304;H01L23/48;H01L23/488 主分类号 H01L25/07
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