CORELESS PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME

摘要

A coreless packaging substrate includes: a circuit buildup structure having at least a dielectric layer, a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the dielectric layer of the circuit buildup structure, a plurality of metal bumps formed on the wiring layer of the circuit buildup structure, and a dielectric passivation layer formed on the surface of the circuit buildup structure and the metal bumps with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip can be enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

主权项

1. A method of fabricating a coreless packaging substrate, comprising the steps of:
providing a carrier board having a plurality of electrical pads formed thereon; forming a circuit buildup structure on the carrier board and the electrical pads, the circuit buildup structure having at least a dielectric layer, at least a wiring layer formed on the at least a dielectric layer, and a plurality of conductive elements formed in the dielectric layer and electrically connected to the at least a wiring layer, wherein the electrical pads are embedded in a lowermost one of the at least a dielectric layer, so as for part of the conductive elements to be electrically connected with the electrical pads; forming a plurality of metal bumps on an uppermost one of the at least a wiring layer; forming a dielectric passivation layer on an uppermost one of the at least a dielectric layer and the uppermost one of the at least a wiring layer for covering the metal bumps; removing a part of the dielectric passivation layer and a part of each of the metal bumps for each of the metal bumps to be formed by a metal column portion and a wing portion integrally connected to the metal column portion, and for an entire top surface of the wing portion of each of the metal bumps to be exposed from the dielectric passivation layer, so as for a semiconductor chip to be electrically connected to the exposed wing portions of the metal bumps; and removing the carrier board for exposing the electrical pads from the lowermost one of the at least a dielectric layer.