发明名称 |
10T Non-Volatile Static Random-Access Memory |
摘要 |
A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed. |
申请公布号 |
US2016111159(A1) |
申请公布日期 |
2016.04.21 |
申请号 |
US201514886663 |
申请日期 |
2015.10.19 |
申请人 |
Cypress Semiconductor Corporation |
发明人 |
Tandingan Joseph S.;Ashokkumar Jayant;Still David;Siman Jesse J. |
分类号 |
G11C14/00;G11C16/14;G11C16/04 |
主分类号 |
G11C14/00 |
代理机构 |
|
代理人 |
|
主权项 |
1. A memory comprising:
an array of non-volatile Static Random Access Memory (nvSRAM) cells, each nvSRAM cell comprising:
a volatile charge storage circuit; anda non-volatile charge storage circuit comprising exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). |
地址 |
San Jose CA US |