CRYPTOGRAPHIC DEVICE FOR IMPLEMENTING S-BOX

摘要

Provided is a cryptographic device implementing an S-Box of an encryption algorithm using a many-to-one binary function. The cryptographic device includes: arrays of first logic gates including I first logic gates which each receive 2 bits of an input signal; 2N second logic gates which each receive corresponding J bits from among I bits output from the arrays of the first logic gates; and L third logic gates which each receive K bits from among 2N bits output from the second logic gates, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, and wherein the N, I, J, K, and L are positive integers. Because a signal output from each array includes only one active bit, current is always consumed constantly to prevent internal data from leaking out to a hacker.

主权项

1. An integrated circuit (IC) having a cryptographic function, the IC comprising:
a plurality of first circuit logic gates configured to receive an input signal having a plurality of bits; a plurality of second circuit logic gates, each of the plurality of second circuit logic gates being configured to receive outputs of corresponding first circuit logic gates; a plurality of third circuit logic gates, each of the plurality of third circuit logic gates being configured to receive outputs of corresponding second circuit logic gates; and an encoder configured to receive outputs of the plurality of third circuit logic gates and to output an encoded signal having a plurality of bits, wherein each of a plurality of values of the encoded signal corresponds to at least two values of a plurality of values of the input signal, each value of the encoded signal being represented by the plurality of bits of the encoded signal, each value of the input signal being represented by the plurality of bits of the input signal, wherein, for any value of the plurality of bits of the input signal, a predetermined number of the first circuit logic gates from among the plurality of first circuit logic gates output logic “1” and the remaining first circuit logic gates output logic “0”, wherein, for any value of the plurality of bits of the input signal, a predetermined number of the second circuit logic gates from among the plurality of second circuit logic gates output logic “1” and the remaining second circuit logic gates output logic “0”, and wherein, for any value of the plurality of bits of the input signal, a predetermined number of the third circuit logic gates from among the plurality of third circuit logic gates output logic “1” and the remaining third circuit logic gates output logic “0”.