Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory

摘要

Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.

主权项

1. A method for operating a memory device, comprising:
performing a programming operation involving a set of memory cells, each memory cell of the set of memory cells comprises a charge-trapping layer, a control gate, a drain, a source and a channel, and the performing the programming operation comprises configuring the memory cells to provide a positive gate-to-channel voltage for the memory cells, the configuring the memory cells to provide the positive gate-to-channel voltage comprises applying a program voltage to the control gates of the memory cells; in response to completion of the programming operation, performing a data retention operation which configures the memory cells to provide a negative gate-to-channel voltage for the memory cells; wherein:
the memory cells are in NAND strings;the NAND strings comprise drain-side select gate transistors; andthe configuring the memory cells to provide the negative gate-to-channel voltage comprises applying a drain voltage to drains of the drain-side select gate transistors and a control gate voltage to control gates of the drain-side select gate transistors which cause the drain-side select gate transistors to charge up the channels by gate-induced drain leakage; and performing an erase operation for the set of memory cells, the performing the erase operation comprises applying a drain voltage to the drains of the drain-side select gate transistors and a control gate voltage to the control gates of the drain-side select gate transistors which cause the drain-side select gate transistors to charge up the channels by gate-induced drain leakage, wherein the drain voltage applied to the drains of the drain-side select gate transistors in the data retention operation is lower than the drain voltage applied to the drains of the drain-side select gate transistors in the erase operation.