NOVEL LOW COST, LOW POWER HIGH PERFORMANCE SMP/ASMP MULTIPLE-PROCESSOR SYSTEM

摘要

A processing system includes multiple processors in which first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). A third processor may be included that also operates at the first clock frequency and the first supply voltage at all times. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. A controller enables control and fast-switching between the two modes for the switchable processor. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control a voltage supply and CPU/memory clock to the switchable processor and cache memory.

主权项

1. A multi-processor (MP) processing system, comprising:
a plurality of processors comprising,
a first processor configured to receive and operate in accordance with a first clock signal having a first predetermined frequency and a first supply voltage having a first predetermined operating voltage, anda second processor configured to receive and operate in accordance with either the first clock signal or a second clock signal having a second predetermined frequency different from the first predetermined frequency and receive and operate in accordance with a second supply voltage having a second predetermined operating voltage different from the first predetermined operating voltage; a controller coupled to at least the second processor and configured to switch operation of the second processor between a first mode of operation and a second mode of operation, wherein:
when in the first mode of operation, the second processor receives and operates in accordance with the first clock signal and the first supply voltage, andwhen in the second mode of operation, the second processor receives and operates in accordance with the second clock signal and the second supply voltage; and wherein the first processor is further configured to only receive and operate in accordance with the first clock signal and the first supply voltage during both the first mode and second mode of operation.