发明名称 COMMON CONTACT OF N++ AND P++ TRANSISTOR DRAIN REGIONS IN CMOS
摘要 Implementations of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one implementation, an integrated circuit is provided. The integrated circuit comprises a first transistor having a first conductivity type, the first transistor comprising a first gate, an first source region and a first drain region disposed on opposite sides of the first gate, and a second transistor having a second conductivity type opposite from the first conductivity type of the first transistor, the second transistor comprising a second gate, a second source region and a second drain region disposed on opposite sides of the second gate, wherein the second drain region of the second transistor is abutted against the first drain region of the first transistor.
申请公布号 WO2016060841(A1) 申请公布日期 2016.04.21
申请号 WO2015US52976 申请日期 2015.09.29
申请人 APPLIED MATERIALS, INC. 发明人 ADERHOLD, WOLFGANG R.
分类号 H01L21/8238 主分类号 H01L21/8238
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