发明名称 Interfaz periférica serie (serial-peripheral-interface) con reducida cantidad de líneas de conexión
摘要 The system has a master unit (1) connected with a slave unit (2) via a data line (3). A data transfer protocol enables the master unit to transfer a data request signal or clock signal (SCLK) over the data line to the slave unit in a data transmission mode for synchronous data transmission. The protocol enables the slave unit to transfer a data signal as a response to the data request signal or the clock signal to the master unit over the data line. The slave unit is integrated into a sensor and an actuator unit. An independent claim is also included for a method for data transmission between a master unit and a slave unit.
申请公布号 ES2567252(T3) 申请公布日期 2016.04.21
申请号 ES20090753963T 申请日期 2009.05.29
申请人 Continental Teves AG & Co. OHG 发明人 PEICHEL, Thomas;EHRENBERG, Thorsten;SCHRIEFER, Jörn
分类号 H04L12/403;H04L7/00 主分类号 H04L12/403
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