DUMMY METAL STRUCTURE AND METHOD OF FORMING DUMMY METAL STRUCTURE

摘要

Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.

主权项

1. A method comprising:
forming a first metal interconnection layer above a substrate of a semiconductor wafer and between a plurality of die regions, the first metal interconnection layer including a first plurality of dummy vertical interconnect accesses (VIAs) and a first plurality of dummy metal lines, wherein the first plurality of dummy metal lines laterally connect the first plurality of dummy VIAs; forming a second metal interconnection layer above the first metal interconnection layer and between the plurality of die regions, the second metal interconnection layer including a second plurality of dummy VIAs and a second plurality of dummy metal lines, wherein the second plurality of dummy VIAs vertically connect the first plurality of dummy metal lines with the second plurality of dummy metal lines, and the second plurality of dummy metal lines laterally connect the second plurality of dummy VIAs; and forming one or more of the first metal interconnection layer and the second metal interconnection layer, in alternating order, in forming remaining metal interconnection layers of the semiconductor wafer.